/*
 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
 *
 * Based on:
 *
 * -------------------------------------------------------------------------
 *
 *  linux/include/asm-arm/arch-davinci/hardware.h
 *
 *  Copyright (C) 2006 Texas Instruments.
 *
 *  This program is free software; you can redistribute  it and/or modify it
 *  under  the terms of  the GNU General  Public License as published by the
 *  Free Software Foundation;  either version 2 of the  License, or (at your
 *  option) any later version.
 *
 *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
 *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
 *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
 *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
 *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
 *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
 *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 *  You should have received a copy of the  GNU General Public License along
 *  with this program; if not, write  to the Free Software Foundation, Inc.,
 *  675 Mass Ave, Cambridge, MA 02139, USA.
 *
 */
#ifndef __ASM_ARCH_HARDWARE_H
#define __ASM_ARCH_HARDWARE_H

#include "rtthread.h"

#define	REG(addr)	(*(volatile unsigned int *)(addr))
#define REG_P(addr)	((volatile unsigned int *)(addr))

#define readb(a)	(*(volatile rt_uint8_t*)(a))
#define readw(a)	(*(volatile rt_uint16_t*)(a))
#define readl(a)	(*(volatile rt_uint32_t*)(a))

#define writeb(v,a)	(*(volatile rt_uint8_t*)(a) = (v))
#define writew(v,a)	(*(volatile rt_uint16_t*)(a) = (v))
#define writel(v,a)	(*(volatile rt_uint32_t*)(a) = (v))

typedef volatile unsigned int	dv_reg;
typedef volatile unsigned int *	dv_reg_p;

/*
 * Base register addresses
 *
 * NOTE:  some of these DM6446-specific addresses DO NOT WORK
 * on other DaVinci chips.  Double check them before you try
 * using the addresses ... or PSC module identifiers, etc.
 */
#if defined(CONFIG_SOC_DM646X)
#define DAVINCI_DMA_3PCC_BASE			(0x01c00000)
#define DAVINCI_DMA_3PTC0_BASE			(0x01c10000)
#define DAVINCI_DMA_3PTC1_BASE			(0x01c10400)
#define DAVINCI_DMA_3PTC2_BASE			(0x01c10800)
#define DAVINCI_DMA_3PTC3_BASE			(0x01c10c00)
//reserved
#define DAVINCI_VIDEO_PORT_BASE			(0x01c12000)
//reserved
#define DAVINCI_VDCE_BASE				(0x01c12800)
#define DAVINCI_TSIF0_BASE				(0x01c13000)
#define DAVINCI_TSIF1_BASE				(0x01c13400)
//reserved
#define DAVINCI_UART0_BASE				(0x01c20000)
#define DAVINCI_UART1_BASE				(0x01c20400)
#define DAVINCI_UART2_BASE				(0x01c20800)
//reserved
#define DAVINCI_I2C_BASE				(0x01c21000)
#define DAVINCI_TIMER0_BASE				(0x01c21400)
#define DAVINCI_TIMER1_BASE				(0x01c21800)
#define DAVINCI_TIMER2_BASE				(0x01c21c00)
#define DAVINCI_PWM0_BASE				(0x01c22000)
#define DAVINCI_PWM1_BASE				(0x01c22400)
//reserved
#define DAVINCI_CRGEN0_BASE				(0x01c26000)
#define DAVINCI_CRGEN1_BASE				(0x01c26400)
//reserved
#define DAVINCI_SYSTEM_MODULE_BASE		(0x01c40000)
#define DAVINCI_PLL_CNTRL1_BASE			(0x01c40800)
#define DAVINCI_PLL_CNTRL2_BASE			(0x01c40c00)
#define DAVINCI_PWR_SLEEP_CNTRL_BASE	(0x01c41000)
//reserved
#define DAVINCI_ARM_INTC_BASE			(0x01c48000)
//reserved
#define DAVINCI_USB_OTG_BASE			(0x01c64000)
#define DAVINCI_ATA_BASE				(0x01c66000)
#define DAVINCI_SPI_BASE				(0x01c66800)
#define DAVINCI_GPIO_BASE				(0x01c67000)
#define DAVINCI_HPI_BASE				(0x01c67800)
//reserved
#define DAVINCI_EMAC_CONTROL_BASE		(0x01c80000)
#define DAVINCI_EMAC_CONTROL_MODULE_BASE	(0x01c81000)
#define DAVINCI_EMAC_CTRL_MODULE_RAM_BASE	(0x01c82000)
#define DAVINCI_MDIO_BASE					(0x01c84000)
//reserved
#define DAVINCI_McASP0_BASE					(0x01d01000)
#define DAVINCI_McASP0_DATA_BASE			(0x01d01400)
#define DAVINCI_McASP1_BASE					(0x01d01800)
#define DAVINCI_MCASP1__DATA_BASE			(0x01d01c00)
#elif defined(CONFIG_SOC_DM36X)
#define DAVINCI_DMA_3PCC_BASE			(0x01c00000)
#define DAVINCI_DMA_3PTC0_BASE			(0x01c10000)
#define DAVINCI_DMA_3PTC1_BASE			(0x01c10400)
#define DAVINCI_DMA_3PTC2_BASE			(0x01c10800)
#define DAVINCI_DMA_3PTC3_BASE			(0x01c10c00)
//reserved
#define DAVINCI_UART0_BASE				(0x01c20000)
//reserved
#define DAVINCI_TIMER3_BASE				(0x01c20800)
#define DAVINCI_REAL_TIME_OUT_BASE		(0x01c20c00)
#define DAVINCI_I2C_BASE				(0x01c21000)
#define DAVINCI_TIMER0_BASE				(0x01c21400)
#define DAVINCI_TIMER1_BASE				(0x01c21800)
#define DAVINCI_TIMER2_BASE				(0x01c21c00)
#define DAVINCI_PWM0_BASE				(0x01c22000)
#define DAVINCI_PWM1_BASE				(0x01c22400)
#define DAVINCI_PWM2_BASE				(0x01c22800)
#define DAVINCI_PWM3_BASE				(0x01c22c00)
#define DAVINCI_SPI4_BASE				(0x01c23000)
#define DAVINCI_TIMER4_BASE				(0x01c23800)
#define DAVINCI_ADCIF_BASE				(0x01c23c00)
//reserved
#define DAVINCI_SYSTEM_MODULE_BASE		(0x01c40000)
#define DAVINCI_PLL_CNTRL1_BASE			(0x01c40800)
#define DAVINCI_PLL_CNTRL2_BASE			(0x01c40c00)
#define DAVINCI_PWR_SLEEP_CNTRL_BASE	(0x01c41000)
//reserved
#define DAVINCI_ARM_INTC_BASE			(0x01c48000)
//reserved
#define DAVINCI_USB_OTG_BASE			(0x01c64000)
#define DAVINCI_SPI0_BASE				(0x01c66000)
#define DAVINCI_SPI1_BASE				(0x01c66800)
#define DAVINCI_GPIO_BASE				(0x01c67000)
#define DAVINCI_SPI2_BASE				(0x01c67800)
#define DAVINCI_SPI3_BASE				(0x01c68000)
//reserved
#define DAVINCI_PRTCSS_INTERFACE_BASE	(0x01c69000)
#define DAVINCI_KEYSCAN_BASE			(0x01c69400)
#define DAVINCI_HPI_BASE				(0x01c69800)

#define DAVINCI_VPSS_REGS_BASE			(0x01c70000)

#define DAVINCI_MMC_SD1_BASE			(0x01d00000)
#define DAVINCI_UART1_BASE				(0x01d06000)
#define DAVINCI_ASYNC_EMIF_CNTRL_BASE	(0x01d10000)
#define DAVINCI_MMC_SD0_BASE			(0x01d11000)

#elif defined(CONFIG_SOC_DA8XX)

#elif defined(CONFIG_SOC_DM644X)

#endif

void davinci_enable_uart0(void);
void davinci_enable_emac(void);
void davinci_enable_i2c(void);
void davinci_errata_workarounds(void);

#ifndef CONFIG_SOC_DA8XX

#define VDD3P3V_PWDN			(0x01c40048)
#define UART0_PWREMU_MGMT		(0x01c20030)

#define PSC_SILVER_BULLET		(0x01c41a20)

#else /* CONFIG_SOC_DA8XX */

#define PSC_PSC0_MODULE_ID_CNT		16
#define PSC_PSC1_MODULE_ID_CNT		32

struct davinci_psc_regs {
	dv_reg	revid;
	dv_reg	rsvd0[71];
	dv_reg	ptcmd;
	dv_reg	rsvd1;
	dv_reg	ptstat;
	dv_reg	rsvd2[437];
	union {
		struct {
			dv_reg	mdstat[PSC_PSC0_MODULE_ID_CNT];
			dv_reg	rsvd3[112];
			dv_reg	mdctl[PSC_PSC0_MODULE_ID_CNT];
		} psc0;
		struct {
			dv_reg	mdstat[PSC_PSC1_MODULE_ID_CNT];
			dv_reg	rsvd3[96];
			dv_reg	mdctl[PSC_PSC1_MODULE_ID_CNT];
		} psc1;
	};
};

#define davinci_psc0_regs ((struct davinci_psc_regs *)DAVINCI_PSC0_BASE)
#define davinci_psc1_regs ((struct davinci_psc_regs *)DAVINCI_PSC1_BASE)

#endif /* CONFIG_SOC_DA8XX */

#ifndef CONFIG_SOC_DA8XX

/* Miscellania... */
#define VBPR				(0x20000020)

/* NOTE:  system control modules are *highly* chip-specific, both
 * as to register content (e.g. for muxing) and which registers exist.
 */
#define PINMUX0				0x01c40000
#define PINMUX1				0x01c40004
#define PINMUX2				0x01c40008
#define PINMUX3				0x01c4000c
#define PINMUX4				0x01c40010

#else /* CONFIG_SOC_DA8XX */

struct davinci_pllc_regs {
	dv_reg	revid;
	dv_reg	rsvd1[56];
	dv_reg	rstype;
	dv_reg	rsvd2[6];
	dv_reg	pllctl;
	dv_reg	ocsel;
	dv_reg	rsvd3[2];
	dv_reg	pllm;
	dv_reg	prediv;
	dv_reg	plldiv1;
	dv_reg	plldiv2;
	dv_reg	plldiv3;
	dv_reg	oscdiv;
	dv_reg	postdiv;
	dv_reg	rsvd4[3];
	dv_reg	pllcmd;
	dv_reg	pllstat;
	dv_reg	alnctl;
	dv_reg	dchange;
	dv_reg	cken;
	dv_reg	ckstat;
	dv_reg	systat;
	dv_reg	rsvd5[3];
	dv_reg	plldiv4;
	dv_reg	plldiv5;
	dv_reg	plldiv6;
	dv_reg	plldiv7;
	dv_reg	rsvd6[32];
	dv_reg	emucnt0;
	dv_reg	emucnt1;
};

#define davinci_pllc0_regs ((struct davinci_pllc_regs *)DAVINCI_PLL_CNTRL0_BASE)
#define davinci_pllc1_regs ((struct davinci_pllc_regs *)DAVINCI_PLL_CNTRL1_BASE)
#define DAVINCI_PLLC_DIV_MASK	0x1f

#define ASYNC3          get_async3_src()
#define PLL1_SYSCLK2		((1 << 16) | 0x2)
#define DAVINCI_SPI1_CLKID  (cpu_is_da830() ? 2 : ASYNC3)
/* Clock IDs */
enum davinci_clk_ids {
	DAVINCI_SPI0_CLKID = 2,
	DAVINCI_UART2_CLKID = 2,
	DAVINCI_MDIO_CLKID = 4,
	DAVINCI_ARM_CLKID = 6,
	DAVINCI_PLLM_CLKID = 0xff,
	DAVINCI_PLLC_CLKID = 0x100,
	DAVINCI_AUXCLK_CLKID = 0x101
};

int clk_get(enum davinci_clk_ids id);

/* Boot config */
struct davinci_syscfg_regs {
	dv_reg	revid;
	dv_reg	rsvd[13];
	dv_reg	kick0;
	dv_reg	kick1;
	dv_reg	rsvd1[56];
	dv_reg	pinmux[20];
	dv_reg	suspsrc;
	dv_reg	chipsig;
	dv_reg	chipsig_clr;
	dv_reg	cfgchip0;
	dv_reg	cfgchip1;
	dv_reg	cfgchip2;
	dv_reg	cfgchip3;
	dv_reg	cfgchip4;
};

#define davinci_syscfg_regs \
	((struct davinci_syscfg_regs *)DAVINCI_BOOTCFG_BASE)

/* Emulation suspend bits */
#define DAVINCI_SYSCFG_SUSPSRC_EMAC		(1 << 5)
#define DAVINCI_SYSCFG_SUSPSRC_I2C		(1 << 16)
#define DAVINCI_SYSCFG_SUSPSRC_SPI0		(1 << 21)
#define DAVINCI_SYSCFG_SUSPSRC_SPI1		(1 << 22)
#define DAVINCI_SYSCFG_SUSPSRC_UART2		(1 << 20)
#define DAVINCI_SYSCFG_SUSPSRC_TIMER0		(1 << 27)

/* Interrupt controller */
struct davinci_aintc_regs {
	dv_reg	revid;
	dv_reg	cr;
	dv_reg	dummy0[2];
	dv_reg	ger;
	dv_reg	dummy1[219];
	dv_reg	ecr1;
	dv_reg	ecr2;
	dv_reg	ecr3;
	dv_reg	dummy2[1117];
	dv_reg	hier;
};

#define davinci_aintc_regs ((struct davinci_aintc_regs *)DAVINCI_INTC_BASE)

struct davinci_uart_ctrl_regs {
	dv_reg	revid1;
	dv_reg	revid2;
	dv_reg	pwremu_mgmt;
	dv_reg	mdr;
};

#define DAVINCI_UART_CTRL_BASE 0x28
#define DAVINCI_UART0_CTRL_ADDR (DAVINCI_UART0_BASE + DAVINCI_UART_CTRL_BASE)
#define DAVINCI_UART1_CTRL_ADDR (DAVINCI_UART1_BASE + DAVINCI_UART_CTRL_BASE)
#define DAVINCI_UART2_CTRL_ADDR (DAVINCI_UART2_BASE + DAVINCI_UART_CTRL_BASE)

#define davinci_uart0_ctrl_regs \
	((struct davinci_uart_ctrl_regs *)DAVINCI_UART0_CTRL_ADDR)
#define davinci_uart1_ctrl_regs \
	((struct davinci_uart_ctrl_regs *)DAVINCI_UART1_CTRL_ADDR)
#define davinci_uart2_ctrl_regs \
	((struct davinci_uart_ctrl_regs *)DAVINCI_UART2_CTRL_ADDR)

/* UART PWREMU_MGMT definitions */
#define DAVINCI_UART_PWREMU_MGMT_FREE	(1 << 0)
#define DAVINCI_UART_PWREMU_MGMT_URRST	(1 << 13)
#define DAVINCI_UART_PWREMU_MGMT_UTRST	(1 << 14)

static inline int cpu_is_da830(void)
{
	unsigned int jtag_id	= REG(JTAG_ID_REG);
	unsigned short part_no	= (jtag_id >> 12) & 0xffff;

	return ((part_no == 0xb7df) ? 1 : 0);
}
static inline int cpu_is_da850(void)
{
	unsigned int jtag_id    = REG(JTAG_ID_REG);
	unsigned short part_no  = (jtag_id >> 12) & 0xffff;

	return ((part_no == 0xb7d1) ? 1 : 0);
}

static inline int get_async3_src(void)
{
	return (REG(&davinci_syscfg_regs->cfgchip3) & 0x10) ?
			PLL1_SYSCLK2 : 2;
}

#endif /* CONFIG_SOC_DA8XX */

#endif /* __ASM_ARCH_HARDWARE_H */
